译码器设计实验

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欲获得源码及工程文件，请访问：https://github.com/Chaos-xBug/decoder_74LS138

实验要求

1. 使用行为描述来实现 74LS138 3:8 译码器模块
2. 仿真验证，确保译码器模块逻辑正确
3. 配置 FPGA 管脚
4. 板极验证

具体实验

选择 xc7a100tlcsg324-2L 板卡型号

译码器模块

`timescale 1ns / 1ps
module decoder(G1, G2A, G2B, A, Y);
    input G1, G2A, G2B;
    input [2:0]A;
    output reg [7:0]Y;

    always @(G1, G2A, G2B, A) begin
        if({G1, G2A, G2B} == 3'b100)
            begin
                case(A)
                    3'b000: Y=8'b1111_1110;
                    3'b001: Y=8'b1111_1101;
                    3'b010: Y=8'b1111_1011;
                    3'b011: Y=8'b1111_0111;
                    3'b100: Y=8'b1110_1111;
                    3'b101: Y=8'b1101_1111;
                    3'b110: Y=8'b1011_1111;
                    3'b111: Y=8'b0111_1111;
                    default:Y=8'b1111_1111;
                endcase
            end
        else Y=8'b1111_1111;
    end
endmodule

仿真代码

//~ `New testbench
`timescale  1ns / 1ps  

module tb_decoder;     
    // decoder Inputs
    reg   G1                                   = 0 ;
    reg   G2A                                  = 0 ;
    reg   G2B                                  = 0 ;
    reg   [2:0]  A                             = 0 ;

    // decoder Outputs
    wire  [7:0]  Y                             ;

    decoder  u_decoder (.G1                      ( G1),
        .G2A                     (G2A),
        .G2B                     (G2B),
        .A                       (A    [2:0] ),

        .Y                       (Y    [7:0] )
    );

    initial
    begin
        {G1, G2A, G2B} = 3'b100;
        A = 3'b000;
    end

    always
    begin
        #100;
        A = A + 1'b1;
    end
endmodule

仿真结果

板极验证

管脚约束

set_property IOSTANDARD LVCMOS18 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Y[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports G1]
set_property IOSTANDARD LVCMOS18 [get_ports G2A]
set_property IOSTANDARD LVCMOS18 [get_ports G2B]
set_property PACKAGE_PIN V5 [get_ports G1]
set_property PACKAGE_PIN T4 [get_ports G2A]
set_property PACKAGE_PIN V6 [get_ports G2B]
set_property PACKAGE_PIN T5 [get_ports {A[2]}]
set_property PACKAGE_PIN T6 [get_ports {A[1]}]
set_property PACKAGE_PIN V7 [get_ports {A[0]}]
set_property PACKAGE_PIN U6 [get_ports {Y[7]}]
set_property PACKAGE_PIN R5 [get_ports {Y[6]}]
set_property PACKAGE_PIN U7 [get_ports {Y[5]}]
set_property PACKAGE_PIN R6 [get_ports {Y[4]}]
set_property PACKAGE_PIN R7 [get_ports {Y[3]}]
set_property PACKAGE_PIN U8 [get_ports {Y[2]}]
set_property PACKAGE_PIN T8 [get_ports {Y[1]}]
set_property PACKAGE_PIN V9 [get_ports {Y[0]}]